FIG. 1 (Prior Art) shows a diagram of an architecture 100 for a random access memory implemented on a semiconductor chip. As observed in FIG. 1, the memory architecture includes a “slice” of multiple storage cells 102 each of which store a bit of information for a particular bit line amongst a plurality of bit lines 103. The memory includes a number (N) of such slices 101 equal to the bit width of the words that are read/written from/to the memory. During a read or write operation one, same positioned storage cell in each slice is activated. In the case of a read the activated storage cell provides a bit of information on its corresponding bit line. In the case of a write the activated storage cell receives a bit of information on its corresponding bit line.
Which particular same positioned storage cell is to be activated in each of the slices 101 by any particular memory access is determined by the address decoder 104. Here, the address decoder 104 receives an incoming address 105 and, in response, activates one of the wordlines wl_0 to wl_M−1. As each wordline is coupled to a same positioned storage cell across all of the slices 101, the activation of one wordline in response to an address effectively enables one storage cell for each bit of the incoming/outgoing data word. A single memory chip may include just one or multiple instances of the architecture 100 observed in FIG. 1 (Prior Art). In the case of the later, the process of address decoding may include activating and/or deactivating whole sections of the memory that conform to the architecture of FIG. 1 (Prior Art).